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GaIA BIOS Library
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GWA BSP Cconfiguration options. More...
Macros | |
| #define | SPI1_IO_RX_IRQ_PRI (0x00) |
| Inlining of Core scan functions Comment this for no_inline version. | |
| #define | SPI1_DMA_RX_IRQ_PRI (0x00) |
| SPI DMA transfer Interrupt Priority. | |
| #define | SPI2_IO_RX_IRQ_PRI (0x00) |
| SPI DAC RX Interrupt Priority. | |
| #define | SPI2_DMA_RX_IRQ_PRI (0x00) |
| SPI DMA transfer Interrupt Priority. | |
| #define | SERIAL_0_IRQ_PRI (0x00) |
| Serial 0 Interrupt priority. | |
| #define | SERIAL_1_IRQ_PRI (0x00) |
| Serial 1 Interrupt priority. | |
| #define | CAN1_TX_IRQ_PRI (0x00) |
| CAN1 TX Interrupt priority. | |
| #define | CAN1_RX0_IRQ_PRI (0x00) |
| CAN1 RX0 Interrupt priority. | |
| #define | CAN2_TX_IRQ_PRI (0x00) |
| CAN2 TX Interrupt priority. | |
| #define | CAN2_RX0_IRQ_PRI (0x00) |
| CAN2 RX0 Interrupt priority. | |
GWA BSP Cconfiguration options.
| #define SPI1_IO_RX_IRQ_PRI (0x00) |
Inlining of Core scan functions Comment this for no_inline version.
Inlining of DigIO access functions Comment this for no_inline version SPI Daisy Chain RX Interrupt Priority