Macros and type definitions for GaIA PHY Driver for NetXDuo. More...

#include <stdint.h>

Data Structures
struct	nx_phy_ioctx_t
	PHY I/O Context Structure. More...
struct	nx_phy_obj_t
	PHY Object Structure. More...
struct	nx_phy_ops_t
	PHY Operations Structure. More...

Macros

#define	PHY_ERROR_NONE 0
	Utils return values.
#define	PHY_ERROR_READ -1
	Read error.
#define	PHY_ERROR_WRITE -2
	Write error.
#define	PHY_ERROR_TIMEOUT -3
	Timeout error.

#define	PHY_RESET_TIMEOUT 500
	PHY settings values.
#define	PHY_POWER_UP 1
#define	PHY_POWER_DOWN 0
#define	PHY_SPEED_100M 1
#define	PHY_SPEED_10M 0
#define	PHY_AUTONEG_ENABLE 1
#define	PHY_AUTONEG_DISABLE 0
#define	PHY_DUPLEX_FULL 1
#define	PHY_DUPLEX_HALF 0
#define	PHY_LINK_UP 1
#define	PHY_LINK_DOWN 0

#define	PHY_CR 0x00U /** Control */
	Register Map.
#define	PHY_SR 0x01U /** Status */
#define	PHY_PHYIDR1 0x02U /** PHY Identifier 1 */
#define	PHY_PHYIDR2 0x03U /** PHY Identifier 2 */
#define	PHY_ANAR 0x04U /** Auto-Negotiation Advertisement */
#define	PHY_ANLPAR 0x05U /** Auto-Neg. Link Partner Ability */
#define	PHY_ANER 0x06U /** Auto-Neg. Expansion */
#define	PHY_ANNP 0x07U /** Auto-Neg. Next Page */
#define	PHY_LPNP 0x08U /** Link Partner Next Page Ability */
#define	PHY_MSCR 0x09U /** Master-Slave Control */
#define	PHY_MSSR 0x0AU /** Master-Slave Status */
#define	PHY_MPSECR 0x0BU /** PSE Control */
#define	PHY_MPSESR 0x0CU /** PSE Status */
#define	PHY_MMDACR 0x0DU /** MMD Access Control */
#define	PHY_MMDAADR 0x0EU /** MMD Access Address Data */
#define	PHY_ESR 0x0FU /** Extended Status */

#define	PHY_CR_RESET 0x8000U /** Software Reset */
	Basic Control Register Bitmasks.
#define	PHY_CR_LOOPBACK 0x4000U /** Loopback mode */
#define	PHY_CR_SPEED_SELECT_LSB 0x2000U /** Speed Select (1=100Mb/s) */
#define	PHY_CR_ANEG_EN 0x1000U /** Auto Negotiation Enable */
#define	PHY_CR_POWER_DOWN 0x0800U /** Power Down */
#define	PHY_CR_ISOLATE 0x0400U /** Isolate Media interface */
#define	PHY_CR_RESTART_ANEG 0x0200U /** Restart Auto Negotiation */
#define	PHY_CR_DUPLEX_MODE 0x0100U /** Duplex Mode (1=Full duplex) */
#define	PHY_CR_COLLISION_TEST 0x0080U /** Collision Test */
#define	PHY_CR_SPEED_SELECT_MSB 0x0040U /** Speed Select */
#define	PHY_CR_UNIDIR_EN 0x0020U /** Unidirectional Enable */

#define	PHY_SR_100B_T4 0x8000U /** 100BASE-T4 Capable */
	Basic Status Register Bitmasks.
#define	PHY_SR_100B_TX_FD 0x4000U /** 100BASE-TX Full Duplex Capable */
#define	PHY_SR_100B_TX_HD 0x2000U /** 100BASE-TX Half Duplex Capable */
#define	PHY_SR_10B_T_FD 0x1000U /** 10BASE-T Full Duplex Capable */
#define	PHY_SR_10B_T_HD 0x0800U /** 10BASE-T Half Duplex Capable */
#define	PHY_SR_100B_T2_FD 0x0400U /** 10BASE-T2 Full Duplex Capable */
#define	PHY_SR_100B_T2_HD 0x0200U /** 10BASE-T2 Half Duplex Capable */
#define	PHY_SR_EXT_STATUS 0x0100U /** Extended Status */
#define	PHY_SR_UNIDIR_ABILITY 0x0080U /** Unidirectional ability */
#define	PHY_SR_NO_PREAMBLE 0x0040U /** Preamble suppression */
#define	PHY_SR_ANEG_COMPLETE 0x0020U /** Auto Negotiation Complete */
#define	PHY_SR_REMOTE_FAULT 0x0010U /** Remote Fault */
#define	PHY_SR_ANEG_ABILITY 0x0008U /** Auto Negotiation Ability */
#define	PHY_SR_LINK_STAT 0x0004U /** Link Status (1=link is up) */
#define	PHY_SR_JABBER_DETECT 0x0002U /** Jabber Detect */
#define	PHY_SR_EXT_CAPAB 0x0001U /** Extended Capability */

#define	PHY_ANAR_NEXT_PAGE 0x8000U /** Next page capable */
	Auto-Negotiation Advertisement Register Bitmasks.
#define	PHY_ANAR_REMOTE_FAULT 0x2000U /** Remote fault supported */
#define	PHY_ANAR_PAUSE 0x0C00U /** Pause */
#define	PHY_ANAR_100B_T4 0x0200U /** 100Base-T4 capable */
#define	PHY_ANAR_100B_TX_FD 0x0100U /** 100MBps full-duplex capable */
#define	PHY_ANAR_100B_TX_HD 0x0080U /** 100MBps half-duplex capable */
#define	PHY_ANAR_10B_TX_FD 0x0040U /** 10MBps full-duplex capable */
#define	PHY_ANAR_10B_TX_HD 0x0020U /** 10MBps half-duplex capable */
#define	PHY_ANAR_SELECTOR_FIELD 0x001FU /** Selector field (0x01==IEEE 802.3) */

#define	PHY_ANLPAR_NEXT_PAGE 0x8000U /** Next page capable */
	Auto-Negotiation Link Partner Ability Register Bitmasks.
#define	PHY_ANLPAR_ACKNOWLEDGE 0x4000U /** Acknowledge from partner */
#define	PHY_ANLPAR_REMOTE_FAULT 0x2000U /** Remote fault detected */
#define	PHY_ANLPAR_PAUSE 0x0C00U /** Pause */
#define	PHY_ANLPAR_100B_TX_FD 0x0100U /** 100MBps full-duplex capable */
#define	PHY_ANLPAR_100B_TX_HD 0x0080U /** 100MBps half-duplex capable */
#define	PHY_ANLPAR_10B_TX_FD 0x0040U /** 10MBps full-duplex capable */
#define	PHY_ANLPAR_10B_TX_HD 0x0020U /** 10MBps half-duplex capable */
#define	PHY_ANLPAR_SELECTOR_FIELD 0x001FU /** Selector field (0x01==IEEE 802.3) */

#define	PHY_ANER_PDF 0x0010U /** Parallel Detection Fault */
	Auto-Negotiation Expansion Register Bitmasks.
#define	PHY_ANER_LPAR_NEXT_PAGE 0x0008U /** Link Partner Next Page Able */
#define	PHY_ANER_NEXT_PAGE 0x0004U /** Next Page Able */
#define	PHY_ANER_PAGE_RECEIVED 0x0002U /** Page Received */
#define	PHY_ANER_LPAR_ANEG 0x0001U /** Link Partner Auto-Negotiation Able */

#define	PHY_ANNP_NEXT_PAGE 0x8000U /** Next Page */
	Auto-Negotiation Next Page Register Bitmasks.
#define	PHY_ANNP_MESSAGE_PAGE 0x2000U /** Message Page */
#define	PHY_ANNP_ACKNOWLEDGE2 0x1000U /** Acknowledge2 */
#define	PHY_ANNP_TOGGLE 0x0800U /** Toggle */
#define	PHY_ANNP_MESSAGE_FIELD 0x07FFU /** Message Field */
#define	PHY_LPNP_NEXT_PAGE 0x8000U /** Next page */
	Link Partner Next Page Ability Register Bitmasks.
#define	PHY_LPNP_ACKNOWLEDGE 0x4000U /** Acknowledge */
#define	PHY_LPNP_MESSAGE_PAGE 0x2000U /** Message Page */
#define	PHY_LPNP_ACKNOWLEDGE2 0x1000U /** Acknowledge2 */
#define	PHY_LPNP_TOGGLE 0x0800U /** Toggle */
#define	PHY_LPNP_MESSAGE_FIELD 0x07FFU /** Message Field */

Detailed Description

Macros and type definitions for GaIA PHY Driver for NetXDuo.

Macro Definition Documentation

◆ PHY_ERROR_NONE

#define PHY_ERROR_NONE 0

Utils return values.

Successful operation

Data Structures

Macros

Detailed Description

Macro Definition Documentation

◆ PHY_ERROR_NONE